1. Field of the Invention
The present invention relates to a memory device. In particular, the present invention provides a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device wherein a bit line contact region and a storage node contact region are formed at substantially the same time, and then a storage node contact hole is formed after a formation of bit line to reduce a height of a finally formed storage node contact plug, thereby increasing a storage node open area and reducing a short circuit between the bit lines.
2. Discussion of the Related Art
According to a method for manufacturing a semiconductor device, a stacked structure of a first interlayer insulating film and a first hard mask layer are formed on a semiconductor substrate having a lower structure such as a gate and a landing plug poly, and the stacked structure is etched to form a bit line contact region.
Next, a metal layer filling up the bit line contact region is formed, and then a second interlayer insulating film and a second hard mask layer are formed and etched using a storage node contact mask as an etching mask to form a storage node contact region.
Thereafter, a polysilicon layer filling up the storage node contact region is formed to form a storage node contact plug connecting the semiconductor substrate.
According to the above method for manufacturing a semiconductor device, a short circuit between the storage node contact and the neighboring bit line occurs during a process forming the storage node contact to cause decrease in yield for manufacturing a semiconductor device. The storage node open area is also reduced according to the conventional method to increase in capacitance of the device. As a result, there is a problem of generating a failure in a DRAM cell operation.